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july 2014 docid026753 rev 1 1 / 31 this is information on a product in full production. www.st.com lnbh25ls lnb supply and control ic with step - up and i2c interface datasheet - production data features ? complete interface between lnb and i2c bus ? built - in dc - dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.5 a) ? selectable output current limi t by external resistor ? compliant with main satellite receiver output voltage specifications (15 programmable levels) ? accurate built - in 22 khz tone generator suits widely accepted standards ? 22 khz tone waveform integrity guaranteed at no load condition ? low drop post regulator and high efficiency step - up pwm with integrated power n - mos allowing low power losses ? overload and overtemperature internal protections with i2c diagnostic bits ? lnb short - circuit dynamic protection ? +/ - 4 kv esd tolerant on output power pins applications ? stb satellite receivers ? tv satellite receivers ? pc card satellite receivers description intended for analog and digital satellite receivers/sat - tv and sat - pc cards, the lnbh25ls is a monolithic voltage regulator and interface ic, assembled in qfn24 (4x4 mm) specifically designed to provide 13/18 v power supply and 22 khz tone signaling to the lnb down - converter in the antenna dish or to the multi - switch box. in this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and i2c standard interf acing. table 1: device summary order code package packing LNBH25LSPQR qfn24 (4x4) tape and reel
contents lnbh25ls 2 / 31 docid026753 rev 1 contents 1 block diagram ................................ ................................ .................. 6 2 application information ................................ ................................ .. 7 2.1 diseqc data encoding (dsqin pin) ................................ ................. 7 2.2 data encoding by external 22 khz tone ttl signal ........................... 7 2.3 data encoding by external diseqc envelope control through the dsqin pin ................................ ................................ ................................ ...... 8 2.4 output current limit selection ................................ ............................. 8 2.5 output voltage selection ................................ ................................ .... 8 2.6 diagnostic and protection functions ................................ .................. 8 2.7 surge protections and tvs diodes ................................ .................... 9 2.8 power - on i2c interface reset and undervoltage lockout .................... 9 2.9 png: input voltage minimum detection ................................ ............. 9 2.10 comp: boost capacitors and inductor ................................ ............... 9 2.11 olf: overcurrent and short - circuit protection and diagnostic .......... 10 2.12 otf: thermal protection and diagnostic ................................ .......... 10 3 pin configuration ................................ ................................ ........... 11 4 maximum ratings ................................ ................................ ........... 13 5 typical application circuits ................................ ........................... 14 6 i2c bus interface ................................ ................................ ............ 16 6.1 data validity ................................ ................................ ..................... 16 6.2 start and stop condition ................................ ................................ .. 16 6.3 byte format ................................ ................................ ...................... 16 6.4 acknowledge ................................ ................................ ................... 16 6.5 transmission without acknowledge ................................ ................. 16 7 i2c interface protocol ................................ ................................ .... 18 7.1 write mode transmission ................................ ................................ . 18 7.2 read mode transmission ................................ ................................ 18 7.3 data registers ................................ ................................ .................. 19 7.4 status registers ................................ ................................ ............... 21 8 electrical characteri stics ................................ .............................. 23 9 package mechanical data ................................ ............................. 27 9.1 qfn24l (4x4 mm) mechanical data ................................ ............... 28
lnbh25ls contents docid026753 rev 1 3 / 31 10 revision history ................................ ................................ ............ 30
list of tables lnbh25ls 4 / 31 docid026753 rev 1 list of tables table 1: device summary ................................ ................................ ................................ ........................... 1 table 2: pin description ................................ ................................ ................................ ............................ 11 table 3: absolute maximum ratings ................................ ................................ ................................ ......... 13 table 4: thermal data ................................ ................................ ................................ ............................... 13 table 5: diseqc 1.x bill of material ................................ ................................ ................................ .......... 14 table 6: data 1 (read/write register. register address = 0x2) ................................ ................................ . 20 table 7: data 2 (read/write register. register address = 0x3) ................................ ................................ . 20 table 8: data 3 (read/write register. register address = 0x4) ................................ ................................ . 20 table 9 : data 4 (read/write register. register address = 0x5) ................................ ................................ . 21 table 10: status 1 (read register. register address = 0x0) ................................ ................................ . 22 table 11 : status 2 (read register. register address = 0x1) ................................ ................................ . 22 table 12: electrical characteristics ................................ ................................ ................................ ........... 23 table 13: output voltage selection table (data1 register, write mode) ................................ ..................... 25 table 14: i2c electrical characteristics ................................ ................................ ................................ ...... 25 table 15: address pin characteristics ................................ ................................ ................................ ....... 26 table 16: qfn24l (4x4 mm) mechanical data ................................ ................................ ......................... 29 table 17: document revision history ................................ ................................ ................................ ........ 30
lnbh25ls list of figures docid026753 rev 1 5 / 31 list of figu res figure 1: block diagram ................................ ................................ ................................ .............................. 6 figure 2: tone enable and disable timing (using external waveform) ................................ ........................ 7 figure 3: tone enable and disable timing (using envelope signal) ................................ ............................ 8 figure 4: surge protection circuit ................................ ................................ ................................ ................ 9 figure 5: pin connections (top view) ................................ ................................ ................................ ......... 11 figure 6: diseqc 1.x application circuit ................................ ................................ ................................ ... 14 figure 7: data validity on the i2c bus ................................ ................................ ................................ ....... 17 figure 8: timing diagram of i2c bus ................................ ................................ ................................ ......... 17 figure 9: acknowledge on the i2c bus ................................ ................................ ................................ ...... 17 figure 10: example of writing procedure starting with first data address 0x2 ................................ ......... 18 figure 11: example of reading procedure starting with first status address 0x0 ................................ ..... 19 figure 12: qfn24l (4x4 mm) package dimensions ................................ ................................ ................. 28 figure 13: qfn24l (4x4) footprint recommended data (mm) ................................ ................................ .. 29
b lock diagram lnbh25ls 6 / 31 docid026753 rev 1 1 block diagram figure 1 : block diagram
lnbh25ls application information docid026753 rev 1 7 / 31 2 application information this ic has a built - in dc - dc step - up converter that, from a single source (8 v to 16 v), generates the voltages (v up ) that let the integrated ldo post - regulator (generating the 13 v /18 v lnb output voltages plus the 22 khz diseqc? tone) to work with a minimum dissipated power of 0.5 w typ. @ 500 ma load (the ldo drop voltage is internally kept at v up - v out = 1 v typ.). the ic is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied v cc drops below a f ixed threshold (4.7 v typ.). the step - up converter soft - start function reduces the inrush current during startup. the ss time is internally fixed at 4 ms typ. to switch from 0 to 13 v and 6 ms typ. to switch from 0 to 18 v. 2.1 diseqc data encoding (dsqin pin) the internal 22 khz tone generator is factory trimmed in accordance to diseqc standards, and can be activated in 3 different ways: 1. by an external 22 khz s ource diseqc data connected to the dsqin logic pin (ttl compatible). in this case the i2c tone control bits must be set: extm = ten = 1 2. by an external diseqc data envelope source connected to the dsqin logic pin. in this case the i2c tone control bits mus t be set: extm = 0 and ten = 1 3. through the ten i2c bit if a 22 khz presence is requested in continuous mode. in this case the dsqin ttl pin must be pulled high and extm bit set to 0 each of the above solutions requires that during the 22 khz tone activ ation and/or diseqc data transmission the lpm bit must be set to 0. 2.2 data encoding by external 22 khz tone ttl signal in order to improv e design flexibility an external tone signal can be input to the dsqin pin by setting the extm bit to 1. the dsqin is a logic input pin which activates the 22 khz tone to the v out pin, by using the lnbh25ls integrated tone generator. the output tone wave forms are internally controlled by the lnbh25ls tone generator in terms of rise/fall time and tone amplitude, while, the external 22 khz signal on the dsqin pin is used to define the frequency and the duty cycle of the output tone. a ttl compatible 22 khz signal is required for the proper control of the dsqin pin function. before sending the ttl signal on the dsqin pin, the extm and ten bits must be previously set to 1. as soon as the dsqin internal circuit detects the 22 khz ttl external signal code, the lnbh25ls activates the 22 khz tone on the v out output with about 1 s delay from ttl signal activation, and it stops with about 60 s delay after the 22 khz ttl signal on dsqin has expired, refer to figure 2: "tone enable a nd disable timing (using external waveform)" . figure 2 : tone enable and disable timing (using external waveform)
application information lnbh25ls 8 / 31 docid026753 rev 1 2.3 data encoding by external diseqc envelope control through the dsqin pin if an external diseqc envelope source is available, it is possible to use the internal 22 khz generator activated during the tone transmission by connecting the diseqc envelope source to the dsqin pin. in this case the i2c tone control bits must be set: extm = 0 and ten = 1. in this way, the internal 22 khz signal is superimposed to the v out dc voltage to generate the lnb output 22 khz tone. during the period in which the dsqin is kept high, the internal control circuit activates the 22 khz tone output. the 22 khz tone on the v out pin is activated with about 6 s delay from the dsqin ttl signal rising edge, and it stops with a delay time in the range from 15 s to 60 s after the 22 khz ttl signal on dsqin has expired, refer to figure 3: "tone enable and disable timing (using envelope signal)" . figure 3 : tone enable and disable timing (using envelope sig nal) 2.4 output current limit selection the linear regulator current limit threshold can be set by an external resistor connected to the isel pin. the resis tor value defines the output current limit by the equation: where rsel is the resistor connected between isel and gnd expressed in k and i lim (typ.) is the typical current limit threshold expressed in ma. i lim can be set up to 750 ma. 2.5 output voltage sele ction the linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal da ta 1 register, see section 7.3: "data registers" and table 13: "output voltage selection table (data1 register, write mode)" for exact programmable values. register writing is accessible via the i2c bus. 2.6 diagnostic and protection functions the lnbh25ls has 3 diagnostic internal functions provided by i2c bus, by reading 3 bits on the statu s1 register (in read mode). all the diagnostic bits are, in normal operation (that is no failure detected), set to low. two diagnostic bits are dedicated to the overtemperature and overload protection status (otf and olf). one bit is dedicated to the input voltage power not good function (png). once olf (or otf or png) bit has been activated (set to 1), it is latched to 1 until relevant cause is removed and a new register reading operation is done.
lnbh25ls application information docid026753 rev 1 9 / 31 2.7 surge protections and tvs diodes the lnbh25ls device is directly connected to the antenna cable in a set - top box. atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage t o the attached devices. surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. this leads to currents or electromagnetic fields causing high voltage or current transients. transient voltage suppressor (tvs) devices are usually placed, as shown in the following schematic, to protect the stb output circuits where the lnbh25ls and other devices are electrically connected to the antenna cable. figure 4 : surge protection circuit for this purpos e we recommend the use of lnbtvsxx surge protection diodes specifically designed by st. the selection of lnbtvs diodes should be based on the maximum peak power dissipation supported by the diode, see the lnbtvs datasheet for further details. 2.8 power - on i2c interface reset and undervoltage lockout the i2c interface built into the lnbh25ls is automatically reset at power - on. as long as th e v cc stays below the undervoltage lockout (uvlo) threshold (4.7 v typ.), the interface does not respond to any i2c command and all data register bits are initialized to zeros, therefore keeping the power blocks disabled. once the v cc rises above 4.8 v typ . the i2c interface becomes operative and the data registers can be configured by the main microprocessor. 2.9 png: input voltage minimum detection when i nput voltage (v cc pin) is lower than lpd (low power diagnostic) minimum thresholds, the png i2c bit is set to 1 and the flt pin is set low. refer to table 12: "electrical characteristics" for threshold details. 2.10 comp: boos t capacitors and inductor the dc - dc converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacito rs (vup pin). for this purpose, one i2c bit in the data 4 register, see comp table 9: "data 4 (read/write register. register address = 0x5)" can be set to 1 or 0 as follows: ? comp = 0 for electrolytic capacitors ? comp = 1 for ceramic capacitors for recommended dc - dc capacitor and inductor values refer to section 5: "typical application circuits" and to the bom in table 5: "diseqc 1.x bill of material" .
application information lnbh25ls 10 / 31 docid026753 rev 1 2.11 olf: overcurrent and short - circuit protection and diagnostic in order to reduce the total power dissipation during an overload or a short - circuit condition, the device is provided with a dynamic short - circuit protection. it is possible to set the short - circuit current protection either statically (simple current clamp) or dynamically by the pcl bit of the i2c data 3 register. when th e pcl (pulsed current limiting) bit is set i o low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for t on time 90 ms, after which the output is set in shutdown for t off time of typic ally 900 ms. simultaneously, the diagnostic olf i2c bit of the system register is set to 1. after this time has elapsed, the output is resumed for a time t on . at the end of t on , if the overload is still detected, the protection circuit cycles again throu gh t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low after a register reading is done. typical t on +t off time is 990 ms and an internal timer determines it. this dynamic operation can greatly reduce the power dissipation in short - circuit condition, still ensuring excellent power - on startup in most conditions. however, there could be some cases in which a highly capacitive load on the output may cause a difficult st artup when the dynamic protection is chosen. this can be solved by initiating any power startup in static mode (pcl=1) and, then, switching to the dynamic mode (pcl=0) after a chosen amount of time depending on the output capacitance. also in static mode, the diagnostic olf bit goes to 1 when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is done. after the overload condition is removed, normal operation can be resumed in two ways, according to the olr i2c bit on the data 4 register. if olr=1, all vsel 1..4 bits are reset to 0 and lnb output (v out pin) is disabled. to re - enable output stage, the vsel bits must be set again by the microprocessor, and the olf bit is reset to 0 after a regist er reading operation. if olr=0, output is automatically re - enabled as soon as the overload condition is removed, and the olf bit is reset to 0 after a register reading operation. 2.12 otf: thermal protection and diagnostic the lnbh25ls is also protected against overheating: when the junction temperature exceeds 150 c (typ.), the step - up converter and the linear regulator are shut off, the diagnostic ot f bit in the status1 register is set to 1. after the overtemperature condition is removed, normal operation can be resumed in two ways, according to the therm i2c bit on the data 4 register. if therm=1, all vsel 1..4 bits are reset to 0 and lnb output (v out pin) is disabled. to re - enable output stage, the vsel bits must be set again by the microprocessor, while the otf bit is reset to 0 after a register reading operation. if therm=0, output is automatically re - enabled as soon as the overtemperature co ndition is removed, while the otf bit is reset to 0 after a register reading operation.
lnbh25ls pin configuration docid026753 rev 1 11 / 31 3 pin configuration figure 5 : pin connections (top view) table 2: pin description pin symbol name function 3 lx n - mos drain integrated n - channel power mosfet drain 4 p - gnd power ground dc - dc converter power ground. to be connected directly to the epad 6 addr address setting two i2c bus addresses available b y setting the address pin level voltage. see table 15: "address pin characteristics" 7 scl serial clock clock from i2c bus 8 sda serial data bi - directional data from/to i2c bus 9 isel current selection the resistor rsel connected between isel and gnd defines the linear regulator current limit threshold. see section 6.5: "transmission without acknowledge" 2,15,18, 19,23 gnd analog ground analog circuits ground. to be connected directly t o the exposed pad 16 byp bypass capacitor needed for internal pre - regulator filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to t he device 17 v cc supply input 8 to 16 v ic dc - dc power supply 20 v out lnb output port output of the integrated very low drop linear regulator. see table 13: "output voltage selection table (data1 register, write mode)" fo r voltage selections and description
pin configuration lnbh25ls 12 / 31 docid026753 rev 1 pin symbol name function 21 v up step - up voltage input of the linear post - regulator. the voltage on this pin is monitored by the internal step - up controller to keep a minimum dropout across the linear pass transistor 22 dsqin dsqin for diseqc envelope input or external 22 khz ttl input it can be used as diseqc envelope input or external 22 khz ttl input depending on the extm i2c bit setting as follows: extm=0, ten=1: it accepts the diseqc envelope code from the main microcontroller. the lnbh25l s uses this code to modulate the internally generated 22 khz carrier. if extm=ten=1: it accepts external 22 khz logic signals which activate the 22 khz tone output, refer to section 2.3: "data encoding by external diseqc env elope control through the dsqin pin" . pull - up high if the tone output is activated only by the ten i2c bit epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat 1, 5, 10, 11, 12, 13, 14, 24 n .c. not internally connected not internally connected pins. these pins can be connected to gnd to improve thermal performance
lnbh25ls maximum ratings docid026753 rev 1 13 / 31 4 maximum ratings table 3: absolute maximum ra tings symbol parameter value unit v cc dc power supply input voltage pins - 0.3 to 20 v v up dc input voltage - 0.3 to 40 v i out output current internally limited ma v out dc output pin voltage - 0.3 to 40 v v i logic input pin voltage (sda, scl, dsqin, addr pins) - 0.3 to 7 v lx lx input voltage - 0.3 to 30 v v byp internal reference pin voltage - 0.3 to 4.6 v isel current selection pin voltage - 0.3 to 3.5 v t stg storage temperature range - 50 to 150 c t j operating junction temperature range - 25 to 125 c esd esd rating with human body model (hbm) all pins, unless power output pins 2 kv esd rating with human body model (hbm) for power output pins 4 table 4: thermal data symbol parameter value unit r thjc thermal resistance junction - case 2 c/w r thja t hermal resistance junction - ambient with device soldered on 2s2p 4 - layer pcb provided with thermal vias below exposed pad 40 c/w absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and f unctional operation of the device at these conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all voltage values are with respect to network ground terminal.
typical application circuits lnbh25ls 14 / 31 docid026753 rev 1 5 typical application ci rcuits figure 6 : diseqc 1.x application circuit table 5: diseqc 1.x bill of material component notes r1 (rsel) smd resistor. refer to table 12: "electrical characteristics" and isel pin description in table 2: "pin description" c1 > 25 v electrolytic capacitor, 100 f or higher is suitable or > 25 v ceramic capacitor, 10 f or higher is suitable c2 with comp = 0, > 25 v electrolytic capacitor, 100 f or higher is suitable or with comp = 1, > 35 v ceramic capacitor, 22 f (or 2 x 10 f) or higher is suitable c3 from 470 nf to 2.2 f ceramic capacitor placed as close as possible to v up pins. higher values allow lower dc - dc noise c5 from 100 nf to 220 nf ceramic capacitor placed as close as possible to v out pins. higher values allow lower dc - dc noise c4, c7 220 nf ceramic capacitors. to be placed as close as possible to v out pin d1 stps130a or similar schottky diode d2 1n4001 - 07, s1a - s1m, or any similar general purpose rectifier
lnbh25ls typi cal application circuits docid026753 rev 1 15 / 31 component notes d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, v rrm > 25 v, v f < 0.5 v. to be placed as close as possible to v out pin l1 with comp=0, use 10 h inductor with i sat > i peak where i peak is the boost converter peak current or with comp=1 and c2 = 22 f, use 6.8 h inductor with i sat > i peak where i peak is the boost converter peak current
i2c bus interface lnbh25ls 16 / 31 docid026753 rev 1 6 i2c bus interface data transmission from the main microprocessor to the lnbh25ls and vice versa takes place through the 2 - wire i2c bus interface, consisting of the 2 - line sda and scl (pull - up resis tors to positive supply voltage must be externally connected). 6.1 data validity as shown in figure 7: "data validity on the i2c bus" , the data on the sda line must be stable during the high semi - period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 8: "timing diagram of i2c bus" , a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of t he sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte mu st be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse, see figure 9: "acknowledge on the i2c bus" . the peripheral (lnbh25ls), which acknowledges, must pull down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this c lock pulse. the peripheral, which has been addressed, has to generate acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the nin th clock pulse time. in this case the master transmitter can generate the sto p information in order to abort the transfer. the lnbh25ls doesnt generate acknowledge if v cc supply is below the undervoltage lockout threshold (4.7 v typ.). 6.5 transmission without acknowledge to a void detect ing the acknowledges of the lnbh25ls, the microprocessor can use a simpler transmission: it simply waits for one clock without checking the slave acknowledging, and sends the new data. this approach i s of course less protected from misworking and decreases noise immunity.
lnbh25ls i2c bus interface docid026753 rev 1 17 / 31 figure 7 : data validity on the i2c bus figure 8 : timing diagram of i2c bus figure 9 : acknowledge on th e i2c bus
i2c interface protocol lnbh25ls 18 / 31 docid026753 rev 1 7 i2c interface protocol 7.1 write mode transmission the lnbh25ls interface protocol is made up of: ? a start condition (s) ? a chip address byte with the lsb bit r/w = 0 ? a register address (internal address of the first register to be accessed) ? a sequence of data (byte to write in the addressed internal register + acknow ledge) ? the following bytes, if any, to be written to successive internal registers ? a stop condition (p). the transfer lasts until a stop bit is encountered ? the lnbh25ls, as slave, acknowledges every byte transfer figure 10 : exa mple of writing procedure starting with first data address 0x2 ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the val ues to select the chip address the writing procedure can start from any register address by simply setting x values in the register address byte (after the chip address). it can be also stopped by the master by sending a stop condition after any acknowledge bit. 7.2 read mode transmission in read mode the byte sequence as follows: ? a start condition (s) ? a chip address byte with the lsb bit r/w=0 ? the register address byte of the internal first register to be accessed ? a stop condition (p) s x x a c k 0 0 x 0 0 0 x r /w = 0 0 0 1 0 0 0 s x x a c k 0 0 x 0 0 0 x r /w = 0 a c k 0 1 0 0 0 vs e l 1 vs e l 3 vs e l 2 n / a n / a n / a vs e l 4 n / a a c k m s b l s b c h i p ad d r e ss m s b l s b r e g i s t e r ad d r e ss m s b l s b c h i p ad d r e ss m s b l s b r e g i s t e r ad d r e ss l p m n/a t en ex t m n / a n / a n / a n / a a c k i set i sw p c l n / a n / a n / a t i m er n / a a c k en_imon olr p a c k n / a n / a n / a n / a t h e r m c o m p p m sb l sb m sb l sb m sb l sb m sb l sb d a t a 1 a d d = 0 x 2 d a t a 2 a d d = 0 x 3 d a t a 3 a d d = 0 x 4 d a t a 4 a d d = 0 x 5 m sb l sb m sb l sb m sb l sb m sb l sb d a t a 1 a d d = 0 x 2 d a t a 2 a d d = 0 x 3 d a t a 3 a d d = 0 x 4 d a t a 4 a d d = 0 x 5 gipg1007141414lm
lnbh25ls i2c interface protocol docid026753 rev 1 19 / 31 ? a new master transmission with th e chip address byte and the lsb bit r/w=1 ? after the acknowledge, the lnbh25ls starts to send the addressed register content. as long as the master keeps the acknowledge low, the lnbh25ls transmits the next address register byte content ? the transmission i s terminated when the master sets the acknowledge high with a following stop bit figure 11 : example of reading procedure starting with first status address 0x0 ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0 /1, set the val ues to select the chip address the writing procedure can start from any register address (status 1 ,2 or data 1..4) by simply setting x values in the register address byte (after the chip address). it can be also stopped by the master by sending a stop condition after any acknowledge bit. 7.3 data registers the data 1..4 registers can be addressed both in write and read mode. in read mode they return the last writing byte status received in the previous write transmission.
i2c interface protocol lnbh25ls 20 / 31 docid026753 rev 1 the following tables provide the register address values of data 1..4 and a function description of each bit. table 6: data 1 (read/write register. register address = 0x2) bit name value description bit 0 (lsb) vsel1 0/1 output voltage selection bits. see table 13: "output voltage selection table (data1 register, write mode)" bit 1 vsel2 0/1 bit 2 vsel3 0/1 bit 3 vsel4 0/1 bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7 (msb) n/a 0 reserved. keep to 0 n/a = reserved bit all bits reset to 0 at power - on table 7: data 2 (read/write register. register address = 0x3) bit name value description bit 0 (lsb) ten 1 22 khz tone enabled. tone output controlled by dsqin pin 0 22 khz tone output disabled bi t 1 n/a 0 reserved. keep to 0 bit 2 extm 1 dsqin input pin is set to receive external 22 khz ttl signal source 0 dsqin input pin is set to receive external diseqc envelope ttl signal bit 3 n/a 0 reserved. keep to 0 bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7 (msb) n/a 0 reserved. keep to 0 n/a = reserved bit all bits reset to 0 at power - on table 8: data 3 (read/write register. register address = 0x4) bit name value description bit 0 (lsb) n/a 1 reserved. keep to 0 bit 1 n/a 0 reserved. keep to 0 bit 2 pcl 1 pulsed (dynamic) lnb output current limiting is deactivated 0 pulsed (dynamic) lnb output current limiting is activated
lnbh25ls i2c interface protocol docid026753 rev 1 21 / 31 bit name value description bit 3 n/a 0 reserved. keep to 0 bit 4 n/ a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7 (msb) n/a 0 reserved. keep to 0 n/a = reserved bit all bits reset to 0 at power - on table 9: data 4 (read/write register. register address = 0x5) bit name value description bit 0 (lsb) n/a 0 reserved. keep to 0 bit 1 n/a 0 reserved. keep to 0 bit 2 n/a 0 reserved. keep to 0 bit 3 olr 1 in case overload protection activation (olf=1), all vsel 1..4 bits are reset to 0 and lnb output (v out pin) is disabled. the vsel bits must be set again by the master after the overcurrent condition is removed (olf=0) 0 in case of overload protection activation (olf=1) the lnb output (v out pin) is automatically enabled as soon as the overload conditions is r emoved (olf=0) with the previous vsel bits setting bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 therm 1 if thermal protection is activated (otf=1), all vsel 1..4 bits are reset to 0 and lnb output (v out pin) is disabled. t he vsel bits must be set again by the master after the overtemperature condition is removed (otf=0) 0 in case of thermal protection activation (otf=1) the lnb output (v out pin) is automatically enabled as soon as the overtemperature condition is removed (otf=0) with the previous vsel bits setting bit 7 (msb) comp 1 dc - dc converter compensation: set to use very low e.s.r. capacitors or ceramic caps on v up pin 0 dc - dc converter compensation: set to use standard electrolytic capacitors on v up pin n/a = reserved bit all bits reset to 0 at power - on 7.4 status registers the status 1, 2 registers can be addressed only in read mode and provide the diagnostic functions describ ed in the following tables.
i2c interface protocol lnbh25ls 22 / 31 docid026753 rev 1 table 10: status 1 (read register. register address = 0x0) bit name value description bit 0 (lsb) olf 1 v out pin overload protection has been triggered (i out > i lim ). refer to table 8: "data 3 (r ead/write register. register address = 0x4)" for the overload operation settings (pcl bit) 0 no overload protection has been triggered to the v out pin (i out < i lim ) bit 1 n/a - reserved bit 2 n/a - reserved bit 3 n/a - reserved bit 4 n/a - reserved bit 5 n/a - reserved bit 6 otf 1 junction overtemperature is detected, t j > 150 c. see also therm bit setting in table 9: "data 4 (read/write register. register address = 0x5)" 0 junction overtemperature not detected , t j < 135 c. t j is below thermal protection threshold bit 7 (msb) png 1 input voltage (v cc pin) lower than lpd minimum thresholds. refer to table 12: "electrical characteristics" 0 input voltage (v cc pin) higher than lpd thresholds. refer to table 12: "electrical characteristics" n/a = reserved bit all bits reset to 0 at power - on table 11: status 2 (read register. register address = 0x1) bit name value description bit 0 (lsb) n/a - r eserved bit 1 n/a - reserved bit 2 n/a - reserved bit 3 n/a - reserved bit 4 n/a - reserved bit 5 n/a - reserved bit 6 n/a - reserved bit 7 (msb) n/a - reserved n/a = reserved bit all bits reset to 0 at power - on
lnbh25ls electrical characteristics docid026753 rev 1 23 / 31 8 electrical characteristics refer to section 5: "typical application circuits" , t j from 0 to 85 c, all data 1..4 register bits set to 0 unless vsel1 = 1, rsel = 11 .5 k, dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see section 6: "i2 c bus interface" . table 12: electrical characteristics symbol parameter test conditions min. typ. max. unit v in supply volta ge (1) 8 12 16 v i in supply current i out = 0 ma 6 ma 22 khz tone enabled (ten=1), dsqin = high, i out = 0 ma 10 ma vsel1=vsel2= vsel3=vsel4=0 1 ma v out output voltage total accuracy valid at any v out selected level - 3.5 +3.5 % v out line regulation v in = 8 to 16 v 40 mv v out load regulation i out from 50 to 750 ma 100 i lim output current limiting thresholds rsel = 11.5 k, iset = 0 750 1100 ma rsel = 16.2 k, iset = 0 500 750 rsel = 22 k, iset = 0 350 550 i lim output current limiting thresholds rsel = 11.5 k, iset = 1 500 ma rsel = 16.2 k, iset = 1 350 rsel = 22 k, iset = 1 250 i sc output short - circuit current rsel = 11.5 k, iset= 0 500 ma ss soft - start time v out from 0 to 13 v 4 ms ss soft - start time v out from 0 to 18 v 6 ms t13 - 18 soft transition rise time v out from 13 to 18 v 1.5 ms t18 - 13 soft transition fall time v out from 18 to 13 v 1.5 ms t off dynamic overload protection off time pcl=0, output shorted 900 ms t on dynamic overload protection on time pcl = timer = 0, output shorted t off /10 pcl = 0, timer = 1, output shorted t off /5 a tone tone amplitude dsqin=high, extm=0, ten=1 i out from 0 to 750 ma c bus from 0 to 750 nf 0.55 0.675 0.8 v pp f ton e tone frequency dsqin=high, extm=0, ten=1 20 22 24 khz d tone tone duty cycle 43 50 57 % tr, tf tone rise or fall time (2) 5 8 15 s eff dc/dc dc - dc converter efficiency i out = 500 ma 93 %
electrical characteristics lnbh25ls 24 / 31 docid026753 rev 1 symbol parameter test conditions min. typ. max. unit f sw dc - dc converter switch ing frequency 440 khz uvlo undervoltage lockout thresholds uvlo threshold rising 4.8 v uvlo threshold falling 4.7 v lp low power diagnostic (lpd) thresholds v lp threshold rising 7.2 v v lp threshold falling 6.7 v il dsqin, pin logic low 0.8 v v ih dsqin, pin logic high 2 v i ih dsqin, pin input current v ih = 5 v 15 a f detin tone detector frequency capture range (3) 0.4 v pp sine wave 19 22 25 khz v detin tone detector input amplitude (3) sine wav e signal, 22 khz 0.3 1.5 v pp z detin tone detector input impedance 150 k v ol_bpsw bpsw pin low voltage i ol_bpsw = 5 ma, dsqin = high, extm=0, ten=1 0.7 v v ol dsqout, flt pin logic low detin tone present, i ol = 2 ma 0.3 0.5 v i oz dsqout, flt pin leakage current detin tone absent, v oh = 6 v 10 a i obk output backward c urrent all vselx=0, v obk = 30 v - 3 - 6 ma i sink output low - side sink current v out forced at v out_nom + 0.1 v 70 ma i sink_ time - out low - side sink current time - out v out forced at v out_nom + 0.1 v pdo i2c bit is set to 1 after this time has elapsed 10 m s i rev max. reverse current v out forced at v out_nom + 0.1 v after pdo bit is set to 1(i sink_time - out elapsed) 2 ma t shdn thermal shutdown threshold 150 c dt shdn thermal shutdown hysteresis 15 c notes: (1) in applications where (v cc - v out ) > 1 .3 v the increased power dissipation inside the integrated ldo must be taken into account in the application thermal management design. (2) guaranteed by design. (3) frequency range in which the detin function is guaranteed. the v pp level is intended on the lnb bus, before the c6 capacitor. see typical application circuit for diseqc 2.x. i out from 0 to 750 ma, c bus from 0 to 750 nf.
lnbh25ls electrical characteristics docid026753 rev 1 25 / 31 table 13: output voltage selection table (data1 register, write mode) vsel4 vsel3 vsel2 vsel1 v out min. v out pin voltage v ou t max. function 0 0 0 0 0.000 v out disabled. the lnbh25ls set in standby mode 0 0 0 1 12.545 13.000 13.455 0 0 1 0 12.867 13.333 13.800 0 0 1 1 13.188 13.667 14.145 0 1 0 0 13.51 14.000 14.490 0 1 0 1 13.832 14.333 14.835 0 1 1 0 14.153 14.66 7 15.180 0 1 1 1 14.475 15.000 15.525 1 0 0 0 17.515 18.150 18.785 1 0 0 1 17.836 18.483 19.130 1 0 1 0 18.158 18.817 19.475 1 0 1 1 18.48 19.150 19.820 1 1 0 0 18.801 19.483 20.165 1 1 0 1 19.123 19.817 20.510 1 1 1 0 19.445 20.150 20.855 1 1 1 1 19.766 20.483 21.200 t j from 0 to 85 c, v i = 12 v table 14: i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in in put current sda, scl, v in = 0.4 to 4.5 v - 10 10 a v ol low level output voltage (1) sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz notes: (1) guaranteed by design.
electrical characteristics lnbh25ls 26 / 31 docid026753 rev 1 t j from 0 to 85 c, v i = 12 v table 15: address pin characteristics symbol parameter test conditions min. typ. max. unit v addr - 1 0001000(r/w) a ddress pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 0 0.8 v v addr - 2 0001001(r/w) a ddress pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 2 5 v
lnbh25ls package mechanical data docid026753 rev 1 27 / 31 9 package mechanical data in order to meet environmental requir ements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark.
package mechanical data lnbh25ls 28 / 31 docid026753 rev 1 9.1 qfn24l (4 x4 mm) mechanical data figure 12 : qfn24l (4x4 mm) package dimensions
lnbh25ls package mechanical data docid026753 rev 1 29 / 31 table 16: qfn24l (4x4 mm) mechanical data dim. mm min. ty p. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.55 2.70 2.80 e 3.90 4.00 4.10 e2 2.55 2.70 2.80 e 0.45 0.50 0.55 l 0.25 0.35 0.40 figure 13 : qfn24l (4x4) footprint recommended data (mm)
revision history lnbh25ls 30 / 31 docid026753 rev 1 10 revision history table 17: document revision history date revision changes 28 - jul - 2014 1 initial release.
lnbh25ls docid026753 rev 1 31 / 31 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely r esponsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resal e of st products with provisions different from the information set forth herein shall void any warranty granted by st for su ch product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owne rs. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics C all rights reserved

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